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HTG2150
8-Bit 320 Pixel Dot Matrix LCD MCU Series
Features
* Operating voltage: 2.4V~3.6V * 16K16 bits program ROM * 1928 bits data RAM * 8~12 bidirectional I/O lines * 8 common33~40 segment LCD driver * One 16-bit programmable timer with overflow inter* Watchdog Timer * On-chip RC oscillator for system clock and 32768Hz
crystal oscillator for timebase and LCD driver
* HALT function and wake-up feature reduce power
consumption
* 8-level subroutine nesting * Bit manipulation instructions * 63 powerful instructions * One interrupt input * 100-pin QFP package
rupts
* One 8-bit programmable timer with 8 stage prescaler
for PFD
* One 8-bit programmable timer with 8 stage prescaler
for Time base
* One 8-bit PWM audio output to directly drive speaker
and buzzer
General Description
The HTG2150 is an 8-bit high performance RISC-like microcontroller. The single cycle instruction and two-stage pipeline architecture make it suitable for high speed application. The device is ideally suited for multiple LCD low power application among which are calculators, clock timer, game, scales, toys and hand held LCD products, as well as for battery systems.
Rev. 1.30
1
May 21, 2002
HTG2150
Block Diagram
S Y S C L K /4 TM R0 STACK0 STACK1 STACK2 P ro g ra m C o u n te r P ro g ra m ROM STACK3 STACK4 STACK5 STACK6 STACK7 In te rru p t C ir c u it TM R2 IN T /S E G 3 7 TM R0C 1 6 b it 8 -s ta g e P r e s c a le r PW MDAC1 M U X U X M PW MDAC2 MP0 MP1 M U X DATA M e m o ry W DTS W D T P r e s c a le r In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r MUX 256 W DTRC OSC TM R2C P.D
SYS CLK PW M1 PW M2
IN T C
In s tr u c tio n R e g is te r
STATUS PAC PA PBC PB PORT B PORT A PA0~PA7
OS RE VD VS S
D
S
CI
ACC
P B 4 ~ P B 7 /S E G 3 3 ~ S E G 3 6
LCD M e m o ry
SYS C LK
8 -s ta g e P r e s c a le r
3 2 7 6 8 H z C ry s ta l LCD D r iv e r TM R3 8 -s ta g e P r e s c a le r M U X
CO M 0~CO M 7
SEG0 PB4~ IN T /S XOUT X IN /S
~S PB EG /S EG
EG 32 7 /S E G 3 3 ~ S E G 3 6 37 EG 38 39
TM R3C
SYS CLK PW M D /A PW MDAC1 PW MDAC2
Rev. 1.30
2
May 21, 2002
HTG2150
Pin Assignment
SE SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81
NC NC NC G9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC
NC NC NC NC NC NC SEG SEG SEG SEG SEG SEG SEG SEG /S E G /S E G /S E G /S E G /S E G /S E G /S E G NC 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 NC NC NC NC NC NC NC
8 9 5 6 7 4 3 2 1
80 79 78 77 76 75 74 73 72
NC NC NC NC NC NC NC SE SE SE SE SE SE SE SE SE CO CO CO CO CO CO CO CO NC NC NC NC NC NC G8 G7 G6 G5 G4 G3 G2 G1 G0 M7 M6 M5 M4 M3 M2 M1 M0
NC
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50
71 70 69 68
PB4 PB5 PB6 PB7 IN T XOUT X IN
HTG 2150 1 0 0 Q . P -A
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC NC NC NC PA PA PA PA PA PA PA PA VS OS VD PW PW RE 0 1 2 3 4 5 6 7 S D S CI M2 M1
NC
NC
Rev. 1.30
3
May 21, 2002
HTG2150
Pad Assignment
SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG9
SEG 25 1
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
SEG 26 2 3 4 5 6 7 8 SEG 27 SEG 28 SEG 29 SEG 30 SEG 31 SEG 32 P B 4 /S E G 3 3
46 45 44 43 42 41 40 9 10 11 12 13 14 15 (0 ,0 ) 39 38 37 36 35 34 33 32 31 30 20 21 OSCI VSS
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
P B 5 /S E G 3 4 P B 6 /S E G 3 5 P B 7 /S E G 3 6 IN T /S E G 3 7 X O U T /S E G 3 8 X IN /S E G 3 9
RES
16
17 PW M1
18 PW M2
19 VDD
22 PA0
23 PA1
24 PA2
25 PA3
26 PA4
27 PA5
28 PA6
29 PA7
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 X -880.45 -887.11 -887.11 -887.11 -887.11 -887.11 -887.11 -887.11 -822.70 -822.70 -822.70 -822.70 Y 1114.46 872.13 765.63 659.03 552.53 445.93 339.43 232.83 103.48 -13.52 -127.52 -244.52 Pad No. 32 33 34 35 36 37 38 39 40 41 42 43 X 882.36 882.36 882.36 882.36 882.36 882.36 882.36 882.36 882.36 882.36 882.36 882.36 Y
Unit: mm
-639.47 -532.87 -426.37 -319.77 -213.27 -106.67 -0.17 106.43 212.93 319.53 426.03 532.63
Rev. 1.30
4
May 21, 2002
HTG2150
Pad No. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 X -824.04 -824.04 -823.97 -871.13 -720.90 -539.25 -404.50 -273.79 -99.06 58.61 175.41 289.41 406.21 520.21 637.01 751.01 867.81 882.36 882.36 Y -354.49 -462.62 -580.52 -1052.80 -1052.80 -1052.80 -1051.65 -1032.67 -1097.34 -1057.70 -1057.70 -1057.70 -1057.70 -1057.70 -1057.70 -1057.70 -1057.70 -852.57 -745.97 Pad No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 X 882.36 882.36 882.36 824.35 717.85 611.25 504.75 398.15 291.65 185.05 78.55 -28.05 -134.55 -241.15 -347.65 -454.25 -560.75 -667.35 -773.85 Y 639.13 745.73 852.23 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46 1114.46
Pad Description
Pad No. 38~62 1~8 Pad Name SEG0~SEG24 SEG25~SEG32 PB4~PB7/ SEG33~SEG36 I/O O I/O or O I or O Mask Option 3/4 Description LCD segment signal output.
9~12
Selectable as bidirectional input/output or LCD segment signal outInput/Output put by mask option. On bidirectional input/output port. Software inor Segment structions determine the CMOS output or Schmitt trigger input with Output pull-high resistor. PB4~PB7 share pad with SEG33~SEG36. Interrupt input or Segment 37 output Crystal or Segment Output 3/4 CMOS CMOS 3/4 3/4 3/4 Wake-up or None Wake-up 3/4 Selectable as external interrupt Schmitt trigger input or LCD segment 37 signal output by mask option. External interrupt Schmitt trigger input with pull-high resistor. Edge triggered activated on a high to low transition. INT shares pad with SEG37. Selectable as 32768Hz crystal oscillator or LCD segment signal output by mask option. Crystal oscillator (32.768kHz) for Timer 3 and LCD clock. XIN shares pad with SEG39; XOUT shares pad with SEG38. Schmitt trigger reset input. Active low without pull-high resistor. Positive PWM CMOS output Negative PWM CMOS output Positive power supply OSCI is connected to the RC network of the internal system clock. Negative power supply, ground Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by mask option. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor. LCD common signal output
13
INT/SEG37
15 14 16 17 18 19 20 21
XIN/SEG39 XOUT/SEG38 RES PWM1 PWM2 VDD OSCI VSS
I or O O I O O 3/4 I 3/4
22~29
PA0~PA7
I/O
37~31
COM7~COM0
O
Rev. 1.30
5
May 21, 2002
HTG2150
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 3.6V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...............................0C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD ISTB1 ISTB2 VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 IOH1 IOH2 IOH3 IOL1 IOL2 IOL3 RPH Parameter Operating Voltage Operating Current (RC OSC) Standby Current With 7mA LCD Bias Option (RTC ON, LCD ON) Standby Current LCD Bias Off Option (RTC OFF, LCD OFF) Input Low Voltage for PA/PB Input High Voltage for PA/PB Input Low Voltage (INT) Input High Voltage (INT) Input Low Voltage (RES) Input High Voltage (RES) Port A, Port B Source Current Segment, Common Output Source Current PWM1/PWM2 Source Current Port A, Port B Sink Current Segment, Common Output Sink Current PWM1/PWM2 Sink Current Pull-high Resistance of PA/PB and INT Test Conditions VDD 3/4 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V Conditions 3/4 No load, fSYS=4MHz No load, HALT mode No load, HALT mode 3/4 3/4 3/4 3/4 3/4 3/4 VOH=2.7V VOH=2.7V VOH=2.7V VOL=0.3V VOL=0.3V VOH=0.3V 3/4 Min. 2.4 3/4 3/4 3/4 0 2.1 0 2.3 3/4 3/4 -1 100 -6 1.5 250 8 30 Typ. 3/4 1 3/4 0.5 3/4 3/4 3/4 3/4 1.5 2.4 -2 200 -8 4 500 10 60 Max. 3.6 2 20 1.5 0.9 3 0.7 3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 120
Ta=25C Unit V mA mA mA V V V V V V mA mA mA mA mA mA kW
A.C. Characteristics
Symbol fSYS tRES tSST tINT Parameter System Clock (RC OSC) Test Conditions VDD 3V 2.4V External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 Power-up or Wake-up from HALT 3/4 Min. 400 400 1 3/4 1 Typ. 3/4 3/4 3/4 1024 3/4
Ta=25C Max. 4000 4000 3/4 3/4 3/4 ms tSYS ms Unit kHz
Note: tSYS=1/fSYS
Rev. 1.30
6
May 21, 2002
HTG2150
Functional Description
Execution flow The system clock for the HTG2150 is derived from an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program counter - PC The 13-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a maximum of 8192 addresses. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
B ank0 B ank1 0000H PC PC+1 PC+2 S ta c k . e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) 1...H 819216 B its 2000H 3...H
S y s te m C lo c k PC
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
1 3 b its P ro g ra m C o u n te r
. e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
. e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
B a n k P o in te r R e g is te r B it5
R O M A d d re s s A 1 3 b it L a tc h
L a tc h d a ta o n E x e c u tio n o f J u m p o r C a ll In s tr u c tio n 1 6 K P r o g r a m R O M A d d r e s s in g A r c h ite c tu r e
Execution flow Mode Initial reset External interrupt Timer counter 0 overflow Timer 2 overflow Timer 3 overflow D/A buffer empty interrupt Skip Loading PCL Jump, call branch Return from subroutine *13 *12 *11 *10 *9 *8 #8 S8 BP.5 #12 #11 #10 #9 S13 S12 S11 S10 S9 Program Rom Address *13 0 0 0 0 0 0 *12 0 0 0 0 0 0 *11 *10 *9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 *7 0 0 0 0 0 0 *6 0 0 0 0 0 0 *5 0 0 0 0 0 0 *4 0 0 0 1 1 1 *3 0 0 1 0 0 1 *2 0 1 0 0 1 0 *1 0 0 0 0 0 0 *0 0 0 0 0 0 0
PC+2 @7 @6 @5 @4 @3 @2 @1 @0 #7 S7 #6 S6 #5 S5 #4 S4 #3 S3 #2 S2 #1 S1 #0 S0
Program rom address Note: *13~*0: Program ROM address @7~@0: PCL bits #12~#0: Instruction code bits Rev. 1.30 7 May 21, 2002 S13~S0: Stack register bits BP.5: Bit 5 of bank pointer (04H)
HTG2150
Program memory - ROM The program memory, which contains executable program instructions, data and table information, is composed of a 16384 x 16 bit format. However as the PC (program counter) is comprised of only 13 bits, the remaining 1 ROM address bit is managed by dividing the program memory into 2 banks, each bank having a range between 0000H and 1FFFH. To move from the present ROM bank to a different ROM bank, the higher 1 bit of the ROM address are set by the BP (Bank Pointer), while the remaining 13 bits of the PC are set in the usual way by executing the appropriate jump or call instruction. As the full 14 address bits are latched during the execution of a call or jump instruction, the correct value of the BP must first be setup before a jump or call is executed. When either a software or hardware interrupt is received, note that no matter which ROM bank the program is in the program will always jump to the appropriate interrupt service address in Bank 0. The original full 14 bit address will be stored on the stack and restored when the relevant RET/RETI instruction is executed, automatically returning the program to the original ROM bank. This eliminates the need for programmers to manage the BP when interrupts occur. Certain locations in Bank 0 of program memory are reserved for special usage:
0000H 0004H 0008H 000CH 010H 014H 018H
* ROM Bank 0 (BP5~BP7=000B)
The ROM bank 0 ranges from 0000H to 1FFFH.
* Location 000H
This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H.
* Location 004H
This area is reserved for the external interrupt service program. If the INT input pin is activated, and the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
This area is reserved for the timer counter 0 interrupt service program. If a timer interrupt results from a timer counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Location 010H/014H
This area is reserved for the timer 2/3 interrupt service program. If a timer interrupt results from a timer 2/3 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H/014H.
* Location 018H
D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t s u b r o u tin e T im e r c o u n te r 0 in te r r u p t s u b r o u tin e U nused T im e r 2 in te r r u p t s u b r o u tin e T im e r 3 in te r r u p t s u b r o u tin e D /A b u ffe r e m p ty in te r r u p t P ro g ra m ROM
This area is reserved for the D/A buffer empty interrupt service program. After the system latch a D/A code at RAM address 28H, the interrupt is enable, and the stack is not full, the program begins execution at location 018H.
* Location 020H
For best condition, this is the starting location for writing the program..
* ROM Bank 1 (BP5~BP7=001B)
The range of the ROM starts from 2000H to 3FFFH.
* Table location
3...H 1 6 b its
Program memory
Any location in the ROM space can be used as look up tables. The instructions TABRDC [m] (use for any bank) and TABRDL [m] (only used for last page of program ROM) transfers the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined. The higher-order byte of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBHP, TBLP) is a read/write register (1FH, 07H), which indicates the table location. Before accessing the table, the location Table Location
Instruction(s) TABRDC [m] TABRDL [m]
*13 #5 1
*12 #4 1
*11 #3 1
*10 #2 1
*9 #1 1
*8 #0 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table location Note: @7~@0: TBLP register bit 7~bit 0 #5~#0: TBHP register bit 13~bit 8 Rev. 1.30 8 May 21, 2002 *13~*0: Current Program ROM table address bit 13~bit 0
HTG2150
must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack register - STACK This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into eight levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter and ROM address A13 bit latch Data are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter and ROM address A13 bit latch Data are restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return address are stored). Data memory - RAM
* Bank 0 (BP4~BP0=00000)
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0C H 0D H 0EH 0.H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1C H 1DH 1EH 1.H 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2.H 30H LCDC COMR LCD C o n tr o l R e g is te r C o m m o n P a d A d d re s s R o ta to r TM R3 TM R3C X 'T A L C PW MC PW M T im e r 3 R e g is te r T im e r 3 C o n tr o l R e g is te r X 't a l . a s t O s c illa t o r u p C o n t r o l PW M PW M C o n tro l D a ta TM R2 TM R2C T im e r 2 R e g is te r T im e r 2 C o n tr o l R e g is te r IN T C H TBHP In te r r u p t C o n tr o l H ig h e r - o r d e r B y te R e g is te r T a b le P o in te r H ig h e r - o r d e r B y te R e g is te r PA PAC PB PBC P A I/O P A I/O P B I/O P B I/O D a ta R e g is te r C o n tr o l R e g is te r D a ta R e g is te r C o n tr o l R e g is te r S p e c ia l P u r p o s e D a ta M e m o ry IA R 0 MP0 IA R 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C TM R0H TM R0L TM R0C P ro g ra m In d ir e c t A d d r e s s in g R e g is te r 0 M e m o r y P o in te r 0 In d ir e c t A d d r e s s in g R e g is te r 1 M e m o r y P o in te r 1 B a n k P o in te r A c c u m u la to r C o u n te r L o w e r - b y te R e g is te r T a b le P o in te r L o w e r - o r d e r B y te R e g is te r T a b le H ig h e r - o r d e r B y te R e g is te r W a tc h d o g T im e r O p tio n S e ttin g R e g is te r S ta tu s R e g is te r In te r r u p t C o n tr o l R e g is te r T im e r C o u n te r 0 H ig h e r - o r d e r B y te R e g is te r T im e r C o u n te r 0 L o w e r - o r d e r B y te R e g is te r T im e r C o u n te r 0 C o n tr o l R e g is te r
3.H 40H
:U nused G e n e ra l P u rp o s e B a n k 0 D a ta M e m o ry (1 9 2 B y te ) R e a d a s "0 0 " P B b it 3 /2 /1 /0 R e a d = 0
..H 80H B a n k 1 5 D a ta M e m o ry (4 0 B y te ) A7H
RAM mapping 0, then it will be turned off. Only MP1 can deal with the memory of this range. The contrast form of RAM location, COMMON, and SEGMENT is as follows. Indirect addressing register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory are pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation.
The Bank 0 data memory includes special purpose and general purpose memory. The special purpose memory is addressed from 00H to 2FH, while general purpose memory is addressed from 40H to FFH. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through the memory pointer registers (MP0;01H, MP1;03H).
* Bank 15 (BP4~BP0=01111B)
The range of RAM starts from 80H to A7H. On the LCD, every bit stands for one dot. If the bit is 1, the light of the dot on the LCD will be turned on. If the bit is Rev. 1.30 9
May 21, 2002
HTG2150
The function of data movement between two indirect addressing registers, is not supported. The memory pointer registers, MP0 and MP1, are 8-bit registers which can be used to access the data memory by combining corresponding indirect addressing registers but Bank 15 can use MP1 only. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and it can carry out immediate data operations. The data movement between two data memories has to pass through the accumulator. LCD driver output The maximum output number of the HTG2150 LCD driver
32Hz 1 512Hz 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5
is 840. The LCD driver bias type is R type, no external capacitor is required and the bias voltage is 1/4 bias. Some of the Segment outputs share pins with another pins, PB4~PB7 (SEG33~SEG36), INT (SEG37), XOUT (SEG38), XIN (SEG39). Whether segment output or I/O pin can individually be decided by mask option. LCD driver output can be enabled or disabled by setting the LCD (bit 6 of LCDC; 2EH) without the influence of the related memory condition. There is a special function for LCD display, which is Rotate function. There are 8 kinds of Rotate function, (user can change the data of the SS0 to SS3.) An example of an lcd driving waveform (1/8 duty, 1/4 bias) is shown below.
COM0
VDD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND VDD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND
COM1
SEG0
VDD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND
L C D d is p la y m e m o r y : (B a n k 1 5 )
A d d re s s COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 80H B it0 B it1 B it2 B it3 B it4 B it5 B it6 B it7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG 17 SEG 18 SEG 39 81H 82H 83H 84H 85H 91H 92H A7H
Rev. 1.30
10
May 21, 2002
HTG2150
Register Bit No. 0~5 6 LCDC 7 RC Label 3/4 LCD Can R/W (Default 000000B) Control the LCD output (0=disable; 1=enabled) (Default=1) LCD clock source select (Default=0) 1= 32768Hz crystal 0= system clock (note*) LCDC register Note: * When the mask option is selected to 32K xtal disable, user should set 0 to LCDC.7 But the 32K xtal cant be disabled in the HT-IDE2000 tools, so user should take care of this difference. Rotate SSL3 SSL2 SSL1 SSL0 x x x x x x x x 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Function
Description The Pad of common 0 is connected to common 0 and the Pad of common 1 is connected to common 1 and so on. The Pad of common 0 is connected to common 1 and the Pad of common 1 is connected to common 2 and so on. The Pad of common 0 is connected to common 2 and the Pad of common 1 is connected to common 3 and so on. The Pad of common 0 is connected to common 3 and the Pad of common 1 is connected to common 4 and so on. The Pad of common 0 is connected to common 4 and the Pad of common 1 is connected to common 5 and so on. The Pad of common 0 is connected to common 5 and the Pad of common 1 is connected to common 6 and so on. The Pad of common 0 is connected to common 6 and the Pad of common 1 is connected to common 7 and so on. The Pad of common 0 is connected to common 7 and the Pad of common 1 is connected to common 0 and so on. 2FH register
Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
* Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
With the exception of the TO and PD flags, bits in the status register can be altered by instructions like any other register. Any data written into the status register will not change the TO or PD flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PD flags can only be changed by system power up, Watchdog Timer overflow, executing the HALT instruction and clearing the Watchdog Timer. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly.
The ALU not only saves the results of a data operation but also changes the status register. Status register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence.
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Labels C Bits 0 Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared when either a system powers up or a CLR WDT instruction is executed. PD is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0. Status register
AC Z OV PD TO 3/4
1 2 3 4 5 6, 7
Interrupt The HTG2150 provides an external interrupt and a PWM D/A interrupt and internal timer interrupts. The Interrupt Control register (INTC;0BH, INTCH;1EH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of the INTC to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupt have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter and A13 bit onto the stack followed by a branch to subroutines at specified locations in the program memory. Only the program counter and A13 bit are pushed onto the stack. If the contents of the register and Status register (STATUS) are altered by Register Bit No. 0 1 2 INTC 3 4 5 6, 7 Label EMI EEI ET0I 3/4 EIF T0F 3/4
the interrupt service program which corrupt the desired control sequence, the contents should be saved first. External interrupt is triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer counter 0 interrupt is initialized by setting the timer counter 0 interrupt request flag (T0F; bit 5 of INTC), resulting from a timer 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The Timer 2/3 interrupts are operated in the same manner as timer 0. While ET2I/ET3I and T2F/T3F are the related control bits and the related request flags of TMR2/TMR3, which locate at bit0/bit1 and bit4/bi5 of the INTCH respectively. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 ( if the stack is not full). To return from the interFunction
Controls the (global) interrupt (1=enable; 0=disable) Controls the external interrupt (1=enable; 0=disable) Controls the timer counter 0 interrupt (1=enable; 0=disable) Unused bit External interrupt request flag (1=active; 0=inactive) Internal timer counter 0 request flag (1=active; 0=inactive) Unused bit INTC register
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Register Bit No. 0 1 2 3 INTCH 4 5 6 7 Label ET2I ET3I PWMI 3/4 T2F T3F PWMF 3/4 Function Controls the Timer 2 interrupt (1=enable; 0=disable) Controls the Timer 3 interrupt (1=enable; 0=disable) PWM D/A interrupt (1=enable; 0=disable) Should be set as 0 always Internal Timer 2 request flag (1=active; 0=inactive) Internal Timer 3 request flag (1=active; 0=inactive) PWM D/A flag (1=active; 0=inactive) Should be set as 0 always INTCH register
rupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the priorities applied are shown in the following table. These can be masked by resetting the EMI bit. No. a b d e f Interrupt Source External interrupt Timer counter 0 overflow Timer 2 overflow Timer 3 overflow PWM D/A interrupt Priority 1 2 4 5 6 Vector 04H 08H 10H 14H 18H
Oscillator configuration There are two oscillator circuits in the HTG2150.
OSCI X IN
32768Hz RC O s c illa to r
XOUT
RTC
O s c illa to r
System and RTC oscillator The RC oscillator signal provides the internal system clock. The HALT mode stops the system oscillator and ignores any external signal to conserve power. Only the RC oscillator is designed to drive the internal system clock. The RTC oscillator provides the Timer 3 and LCD driver clock source. The RC oscillator needs an external resistor connected between OSCI and VSS. The resistance value must range from 50kW to 400kW. However, the frequency of the oscillation may vary with VDD, temperature and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. There is another oscillator circuit designed for the real time clock. In this case, only the 32768Hz crystal can be applied. The crystal should be connected between XIN and XOUT, and two external capacitors are required for the oscillator circuit in order to get a stable frequency. The RTC oscillator is used to provide clock source for the LCD driver and Timer 3. It can be enabled or disabled by mask option. The WDT oscillator is a free running on-chip RC oscillator, requiring no external components. Even if the system enters the power down mode, and the system clock is stopped, the WDT oscillator still runs with a period of approximately 78ms. The WDT oscillator can be disabled by mask option to conserve power.
The timer counter 0 and Timer 2/3 interrupt request flag (T0F/T2F/T3F), External interrupt request flag (EIF), PWM D/A interrupt request flag (PWMF),Enable Timer 0/2/3 bit (ET0I/ET2I/ET3I), enable PWM D/A interrupt (PWMI), Enable external interrupt bit (EEI) and Enable master interrupt bit (EMI) constitute an interrupt control register (INTC/INTCH) which is located at 0BH/1EH in the data memory. EMI, EEI, ET0I, ET2I, ET3I, PWMI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F, T2F, T3F, EIF, PWMF) are set, they will remain in the INTC/INTCH register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the CALL subroutine should not operate in the interrupt subroutine as it will damage the original control sequence.
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Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator). This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to WDT result in no operation. When the internal WDT oscillator (RC oscillator with 78ms period normally) is enable, it is first divided by 256 (8 stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bits 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 WDTS register The WDT overflow under normal operation will initialize chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm reset only the PC and SP are reset to zero. To clear the WDT contents (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instructions, or a HALT instruction. The software instruction is CLR WDT, execution of the CLR WDT instruction will clear the WDT. Power down operation - HALT The HALT mode is initialized by the HALT instruction and results in the following...
W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
* The system oscillator will turn off but the WDT oscilla-
tor keeps running (if the WDT oscillator is selected).
* The contents of the on-chip RAM and registers remain
unchanged.
* WDT and WDT prescaler will be cleared and do re-
counting again.
* All I/O ports maintain their original status. * The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. By examining the TO and PD flags, the reason for chip reset can be determined. The PD flag is cleared when the system powers up or upon executing the CLR WDT instruction and is set when the HALT instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP, the others maintain their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy cycle period will be inserted after the wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in the next instruction execution, this will be executed immediately after a dummy period has finished. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status.
Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
W DT OSC
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
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Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
RES V
DD
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that just resets the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PD and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PD 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Reset circuit
HALT W DT W DT T im e - o u t R eset
W a rm
R eset
RES SST 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tio n C o ld R eset
OSC1
Reset configuration
Note: u means unchanged To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system powers up or awakes from the HALT state. When a system power-up occurs, the SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status are shown below. PC Interrupt Prescaler WDT Timer (0/2/3) LCD Display Pull-high of RESB Input/output Ports SP 000H Disable Clear Clear. After master reset, WDT begins counting Off Enable with Input mode Points to the top of the stack
Timer 0 The timer 0 contains 16-bit programmable count-up counters and the clock source come from the system clock divided by 4. There are three registers related to timer counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH). Writing TMR0L only writes the data into a low byte buffer, and writing TMR0H will write the data and the contents of the low byte buffer into the timer 0 preload register (16-bit) simultaneously. The timer 0 preload register is changed by writing TMR0H operations and writing TMR0L will keep the timer 0 preload register unchanged. Reading TMR0H will also latch the TMR0L into the low byte buffer to avoid the false timing problem. Reading TMR0L returns the contents of the low byte buffer. In other words, the low byte of timer counter 0 cannot be read directly. It must read the TMR0H first to make the low byte contents of timer 0 be latched into the buffer. The TMR0C is the timer 0 control register, which defines the timer 0 options. The timer counter control registers define the operating mode, counting enable or disable and active edge. If the timer counter starts counting, it will count from the current contents in the timer counter to FFFFH. Once an overflow occurs, the counter is reloaded from the timer counter preload register and generates the corresponding interrupt request flag (T0F; bit of INTC) at the same time. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C) should be set to 1. The overflow of the timer counter is one of the wake-up sources. No matter
VDD
RES
S S T T im e - o u t C h ip R eset
tS
ST
Reset timing chart
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what the operation mode is, writing a 0 to ET0I can disable the corresponding interrupt service. In the case of timer counter OFF condition, writing data to the timer counter preload register will also reload that data to the timer counter. But if the timer counter is turned on, data written to the timer counter will only be kept in the timer counter preload register. The timer counter will still operate until overflow occurs. When the timer counter (reading TMR0H) is read, the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration by the programmer.
D a ta B u s T im e r C o u n te r 0 P r e lo a d R e g is te r R e lo a d
S y s te m C lo c k /4
T im e r C o u n te r 0
O v e r flo w T o In te rru p t
L o w B y te B u ffe r
Timer counter 0
The state of the registers is summarized in the following table: Register TMR0H TMR0L TMR0C TMR2 TMR2C TMR3 TMR3C INTCH TBHP Program Counter MP0 MP1 ACC TBLP TBLH STATUS BP LCDC INTC WDTS PA PAC PB PBC COMR PWMC PWM XTALC Note: Reset (Power On) xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 xxxx xxxx 0000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx 0000 0000 0100 0000 0000 0000 0000 0111 1111 1111 1111 1111 1111 0000 1111 0000 0000 0000 1111 1111 xxxx xxxx 0000 0000 WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu 00-0 1000 uuuu uuuu 00-0 1000 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu 0000 0000 0100 0000 0000 0000 0000 0111 1111 1111 1111 1111 1111 0000 1111 0000 0000 0000 1111 1111 xxxx xxxx 0000 0000 uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu 00-0 1000 uuuu uuuu 00-0 1000 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 0100 0000 0000 0000 0000 0111 1111 1111 1111 1111 1111 0000 1111 0000 0000 0000 1111 1111 xxxx xxxx 0000 0000 RES Reset (HALT) uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu 00-0 1000 uuuu uuuu 00-0 1000 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu 0000 0000 0100 0000 0000 0000 0000 0111 1111 1111 1111 1111 1111 0000 1111 0000 0000 0000 1111 1111 xxxx xxxx 0000 0000 WDT Time-out (HALT) uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu 0000H* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
* means warm reset u means unchanged x means unknown
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Label 3/4 TE TON 3/4 TM0, TM1 Bits 0~2 3 4 5 6, 7 Unused bit, read as 0. To define the TMR0 active edge of the timer counter (0=active on low to high; 1=active on high to low) To enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as x. 0, 1=Internal clock TMR0C register Timer 2/3 Timer 2 is an 8-bit counter, and its clock source comes from the system clock divided by an 8-stage prescaler. There are two registers related to Timer 2 ; TMR2 (21H) and TMR2C (22H). Two physical registers are mapped to TMR2 location; writing TMR2 makes the starting value be placed in the Timer 2 preload register and reading the TMR2 gets the contents of the Timer 2 counter. The TMR2C is a control register, which defines the division ratio of the prescaler and counting enable or disable. Writing data to B2, B1 and B0 (bits 2, 1, 0 of TMR2C) can yield various clock sources. Once the Timer 2 starts counting, it will count from the current contents in the counter to FFH. Once an overflow occurs, the counter is reloaded from a preload register, and generates an interrupt request flag (T2F; bit 4 of INTCH). To enable the counting operation, the timer On bit (TON; bit 4 of TMR2C) should be set to 1. For proper operation, bit 6 of TMR2C should be set to 1 and bit 3, bit7 should be set to 0. The Timer 2 can also be used as PFD output by setting PWM1 and PWM2 to be PFD and PFDB output respectively by 2FH.7 and 2FH.6. When the PFD/PFDB function is selected, setting 2FH.4/2FH.5 to 1 will enable the PFD/PFDB output and setting 2FH.4/2FH.5 to 0 will disable the PFD/PFDB output. PFD Frequency: T2f/[256-TMR2)2] Timer 3 has the same structure and operating manner with Timer 2, except for clock source and PFD function. The Timer 3 can be used as a time base to generate a regular internal interrupt. The clock source of Timer 3 can come from RTC OSC (XTAL 32kHz) or system clock divided by an 8-stage prescaler. If the RTC mask option is enabled, a 32kHz crystal is needed across XIN and XOUT pins. The 32kHz signal is processed by an 8-stage prescaler to yield various counting clock for Timer 3. There are 2 registers related to Timer 3; TMR3 (24H) and TMR3C (25H). Writing data to B2, B1, B0 (bit 2, 1, 0 of TMR3C) can yield various counting clock.
D a ta B u s 8 -s ta g e P r e s c a le r T2f TON T im e r 2 O v e r flo w T im e r 2 P r e lo a d R e g is te r R e lo a d
Function
SYS C LK
T o in te r r u p t 2 2 . H .5 2 . H .4 PW MDAC1 2 . H .6 PW MDAC2 2 . H .7 PW M1 PW M2
Timer 2 Label SSL 3~0 PFD PFDB PWM1 PWM2 Bits 3~0 4 5 6 7 LCD common used To enable/disable PFD output (0=disable; 1=enable) To enable/disable PFDB output (0=disable; 1=enable) To select PFDB/PWM1 output (0=PWM1; 1=PFDB) To select PFD/PWM2 output (0=PWM2; 1=PFD) 2FH register Function
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S y s te m C lo c k 8 S ta g e P r e s c a le r m a s k o p tio n .1 3 2 K X 'A T L 2 E H .7 8 S ta g e P r e s c a le r TON 64 .0 near32768H z T3f T im e r 3 L C D D r iv e r (5 1 2 H z ) IN T
P r e lo a d
Timer 3 TMR2C Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 TMR3C Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 F1/2 F1/4 F1/8 F1/16 F1/32 F1/64 F1/128 F1/256
T2f SYS CLK/2 SYS CLK/4 SYS CLK/8 SYS CLK/16 SYS CLK/32 SYS CLK/64 SYS CLK/128 SYS CLK/256
T3f
TMR2C bit 4 to enable/disable timer counting (0=disable;1=enable) TMR2C bit 3 always write 0 TMR2C bit 5 always write 0 TMR2C bit 6 always write 1 TMR2C bit 7 always write 0 F1 can select 4 frequency by mask option Auto Mask Option SYS CLK near 512kHz SYS CLK near 1024kHz SYS CLK near 2048kHz SYS CLK near 4096kHz F0 SYS CLK/16 SYS CLK/32 SYS CLK/64 SYS CLK/128
Time base frequency= T3f / (256 - TMR3) TMR3C bit 4 to enable/disable timer counting (0=disable; 1=enable) TMR3C bit 3 always write 0 TMR3C bit 5 always write 0 TMR3C bit 6 always write 1 TMR3C bit 7 always write 0 Input/output ports There are 12 bidirectional input/output lines in the HTG2150, labeled PA and PB, which are mapped to the data memory of [12H], [14H], respectively. All these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction
DATA Bus D W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
Q CK S Q V
V
DD
DD
W EAK P u ll- u p M a s k O p tio n
D W r ite I/O CK S Q
Q
PA0~PA7 PB4~PB7
M R e a d I/O S y s te m W a k e - u p ( P A o n ly ) M a s k O p tio n U
X
Input/output ports
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MOV A,[m] (m=12H, 14H). For output operation, all data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC) to control the input/output configuration. With this control register, CMOS output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write 1. The pull-high resistance will exhibit automatically if the pull-high option is selected. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H. After a chip reset, these input/output lines stay at schmitt trigger input with pull-high resistor. Each bit of these input/output latches can be set or cleared by the SET [m].i or CLR [m].i (m=12H, 14H) instruction. Some instructions first input data and then follow the output operations. For example, the SET [m].i, CLR [m].i, CPL [m] and CPLA [m] instructions read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability to wake-up the device. Port B are share pad, each pin function are defined by mask option, the PB7 shares with SEG36. The PB6, PB5 and PB4 share with SEG35, SEG34 and SEG33. If the segment output is selected, the related I/O register (PB) cannot be used as general purpose register. Reading the register will result to an unknown state. PWM interface The HTG2150 provides an 8 bit (bit 7 is a sign bit) PWM D/A interface, which is good for speech synthesis. The user can record or synthesize the sound and digitize it into the program ROM. These sound could be played back in sequence of the functions as designed by the internal program ROM. There are several algorithms that can be used in the HTG2150, they are ... PCM, mLAW, DPCM, ADPCM..... . The PWM circuit provides two pad outputs: PWM2, PWM1 which can directly drive a piezo or a 32W speaker without adding any external element. Refer to the Application Circuits. The PWM clock source comes from the system clock divided by a 3-bit prescaler. Setting data to P0, P1 and P2 (bit 3, 4, 5 of 27H) can yield various clock sources. The clock source are use for PWM modulating clock and sampling clock. After setting the start bit (bit 0 27H) and the next falling edge coming from the prescaler, the Rev. 1.30 19 7 bit 6 bit Note: DIV will generate a serial clock to PWM counter for modulating and PWMI for interrupt. The PWM counter latch data at the first F1 clock falling edge and the start counter at F1 rising edge. The F2 clock is synchronous with the first F1 clock and it is also connected to the PWM output latch. In setting the start bit initial status, the PWM1 DAC outputs a high level and change the output status to LOW while the 7 bits counter overflows. BZ/SP 0 0 1 1 Note: 6/7 Bit 0 1 0 1 F1 F0 F0 F0 F0 F2 (Sampling Rate F0/64 F0/128 F0/64 F0/128 Device 32W speaker 32W speaker Buzzer/8W speaker Buzzer/8W speaker
F1: for PWM modulation clock and F2 for sampling clock. F0: system /[n+1] n=0~7 (n:3 bits preload counter)
On the above table, we can easily see that the sampling rate is dependent on the system clock. If start bit is set to 0, the PWM2 and PWM1 will output a GND level voltage. Label D/A BZ/SP Bit Bits 0 1 2 Function D/A control. 0:start ; 1:stop Output driver select 1:Buzzer ; 0:speaker PWM counter bit select 1:7 bits ; 0:6 bits 3 bits preload counter, bit 5/4/3:000B~111B (0~7) bit 3:LSB PWMI D1 0 1 0 1 PWM control register bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 D0 X D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 PWM Interrupt 1 2 4 8
P0~P2 D0, D1 D0 0 0 1 1
3~5 6, 7
X means dont care. bit7: Sign bit PWM data buffer May 21, 2002
HTG2150
.0
S ta r t b it L a tc h .1 .2 O n e s a m p lin g tim e 1 2 8 c lo c k
7 bits PWM counter bit
D a ta B u s
S y s te m
c lo c k
P r e s c a le r .0 .1
P W M D a ta B u ffe r (2 8 H ) V
DD
S ta r t b it 2 7 H .0 PW MI .2
D iv .
CK PE
7 B its C o u n te r O v e r flo w
D CK Q
Q
R
P W M D A C 1 fo r 3 2 W
SPK
P W M D A C 2 fo r 3 2 W
SPK
27H.1=0 speaker
D a ta B u s
S y s te m
c lo c k
P r e s c a le r .0 .1
P W M D a ta B u ffe r (2 8 H ) V
DD
S ta r t b it 2 7 H .0 PW MI .2
D iv .
CK PE
7 B its C o u n te r O v e r flo w
D CK Q
Q
R
S ig n b it P W M D A C 1 fo r B Z P W M D A C 2 fo r B Z
27H.1=1 buzzer
Rev. 1.30
20
May 21, 2002
HTG2150
Mask option The following shows many kinds of mask options in the HTG2150. All the mask options must be defined on order to ensure proper system functioning. No. 1 2 3 Mask Option WDT enable/disable selection. WDT can be enabled or disabled by mask option. Wake-up selection. This option defines the wake-up activity. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT mode by a following edge. External interrupt input pin share with other function selection. INT/SEG37: INT can be set as an external interrupt input pin or LCD segment output pin. I/O pins share with other function selection. PB4/SEG33, PB5/SEG34, PB6/SEG35, PB7/SEG36: PB4, PB5, PB6, PB7 can be set as I/O pins or LCD segment output pins. Segment output pins share with other function selection. XIN/SEG39, XOUT/SEG38: SEG38, SEG39 ban be set as LCD segment output pins or XIN, XOUT pins be connected to a 32768Hz crystal. LCD bias register selection. This option describes the LCD bias current. There are three types of selection. * * Selectable as small, middle or large current.
4
5
6 Note: *
S m a ll c u r r e n t
V 110kW 3 /4 V 110kW 2 /4 V 110kW 1 /4 V 110kW GND
DD DD DD DD
M id d le c u r r e n t
V 60kW 3 /4 V 60kW 2 /4 V 60kW 1 /4 V 60kW GND
DD DD DD DD
L a rg e c u rre n t
V 10kW 3 /4 V 10kW 2 /4 V 10kW 1 /4 V 10kW GND
DD DD DD DD
Rev. 1.30
21
May 21, 2002
HTG2150
Application Circuits
32W s p e a k e r /B u z z e r a p p lic a tio n 8W s p e a k e r a p p lic a tio n
(fS
YS
** 62kW =4M H z)
OSCI C O M 0~C O M 7 SEG 0~SEG 39 (M a x .)
1 /4 B ia s LC D PANEL
(fS
YS
** 62kW =4M H z)
OSCI C O M 0~C O M 7 SEG 0~SEG 39 (M a x .) V
1 /4 B ia s LC D PANEL V
DD
V
PW M1
DD
DD
32W SPK orB uzzer PW M2 RES 0 .1 m . RES PW M2 8050 0 .1 m .
8W SPK
0 .1 m .
*
X IN /S E G 3 9
*
X IN /S E G 3 9
32768Hz
X O U T /S E G 3 8 IN T /S E G 3 7 PA0~PA7
32768Hz
X O U T /S E G 3 8 IN T /S E G 3 7 PA0~PA7
H TG 2150
H TG 2150
Note: * Optional capacitors can be added to get a more accurate frequency. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate value of the external capacitors. ** R=100kW, fSYS=2MHz R=200kW, fSYS=1MHz
Rev. 1.30
22
May 21, 2002
HTG2150
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
Rev. 1.30
23
May 21, 2002
HTG2150
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared. Otherwise the TO and PD flags remain unchanged.
Rev. 1.30
24
May 21, 2002
HTG2150
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 3/4 ADCM A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,x Description Operation Affected flag(s) TC2 3/4 ADDM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Rev. 1.30
25
May 21, 2002
HTG2150
AND A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,x Description Operation Affected flag(s) TC2 3/4 ANDM A,[m] Description Operation Affected flag(s) TC2 3/4 CALL addr Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr
Operation Affected flag(s)
TC2 3/4 CLR [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
26
May 21, 2002
HTG2150
CLR [m].i Description Operation Affected flag(s) TC2 3/4 CLR WDT Description Operation Affected flag(s) TC2 3/4 CLR WDT1 Description TC1 3/4 TO 0 PD 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are cleared. WDT 00H PD and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0*
Operation Affected flag(s)
TC2 3/4 CLR WDT2 Description
TC1 3/4
TO 0*
PD 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0*
Operation Affected flag(s)
TC2 3/4 CPL [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 0*
PD 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Rev. 1.30
27
May 21, 2002
HTG2150
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TC2 3/4 DAA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TC2 3/4 DEC [m] Description Operation Affected flag(s) TC2 3/4 DECA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
Rev. 1.30
28
May 21, 2002
HTG2150
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PD 1 TO 0
Operation
Affected flag(s) TC2 3/4 INC [m] Description Operation Affected flag(s) TC2 3/4 INCA [m] Description Operation Affected flag(s) TC2 3/4 JMP addr Description Operation Affected flag(s) TC2 3/4 MOV A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 0 PD 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Rev. 1.30
29
May 21, 2002
HTG2150
MOV A,x Description Operation Affected flag(s) TC2 3/4 MOV [m],A Description Operation Affected flag(s) TC2 3/4 NOP Description Operation Affected flag(s) TC2 3/4 OR A,[m] Description Operation Affected flag(s) TC2 3/4 OR A,x Description Operation Affected flag(s) TC2 3/4 ORM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
No operation No operation is performed. Execution continues with the next instruction. PC PC+1
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
Rev. 1.30
30
May 21, 2002
HTG2150
RET Description Operation Affected flag(s) TC2 3/4 RET A,x Description Operation Affected flag(s) TC2 3/4 RETI Description Operation Affected flag(s) TC2 3/4 RL [m] Description Operation Affected flag(s) TC2 3/4 RLA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
Rev. 1.30
31
May 21, 2002
HTG2150
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TC2 3/4 RLCA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TC2 3/4 RR [m] Description Operation Affected flag(s) TC2 3/4 RRA [m] Description Operation Affected flag(s) TC2 3/4 RRC [m] Description Operation TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TC2 3/4 Rev. 1.30 TC1 3/4 TO 3/4 PD 3/4 32 OV 3/4 Z 3/4 AC 3/4 C O May 21, 2002
HTG2150
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TC2 3/4 SBC A,[m] Description Operation Affected flag(s) TC2 3/4 SBCM A,[m] Description Operation Affected flag(s) TC2 3/4 SDZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TC2 3/4 SDZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
33
May 21, 2002
HTG2150
SET [m] Description Operation Affected flag(s) TC2 3/4 SET [m]. i Description Operation Affected flag(s) TC2 3/4 SIZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TC2 3/4 SIZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TC2 3/4 SNZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
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May 21, 2002
HTG2150
SUB A,[m] Description Operation Affected flag(s) TC2 3/4 SUBM A,[m] Description Operation Affected flag(s) TC2 3/4 SUB A,x Description Operation Affected flag(s) TC2 3/4 SWAP [m] Description Operation Affected flag(s) TC2 3/4 SWAPA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Rev. 1.30
35
May 21, 2002
HTG2150
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TC2 3/4 TABRDC [m] Description Operation Affected flag(s) TC2 3/4 TABRDL [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
36
May 21, 2002
HTG2150
XOR A,[m] Description Operation Affected flag(s) TC2 3/4 XORM A,[m] Description Operation Affected flag(s) TC2 3/4 XOR A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.30
37
May 21, 2002
HTG2150
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
38
May 21, 2002

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